Multiplier – Wikipedia

In analog electronics, a multiplier is a circuit whose output signal is the product of the instant value of its input signals.

In digital electronics, a multiplier is an electronic circuit performing a multiplication. Multipliers are integrated into most current processors, both to make multiplications between whole numbers and between numbers represented in floating comma.

Multiplier circuit [ modifier | Modifier and code ]

In analog electronics, a multiplier is a circuit whose output signal is the product of the instant value of its input signals ^{[ first ]} .

A multiplier can consist of a differential amplifier circuit, in which the current of the common branch determines the differential gain; It can also exploit the hall effect ^{[ 2 ]} .

On radio, the multiplier, essential for modulation and heterodyne demodulation, is built around a non -linear component (most often a diode.

Frequency multiplier [ modifier | Modifier and code ]

A frequency multiplier is a non -linear circuit, to which a narrow strip signal is applied. The resulting signal has many harmonics of the input frequency. A filter selects that of these multiple frequencies from that of the signal is present at output ^{[ 3 ]} .

Several types of circuits have been offered according to their performance, size and energy consumption. We can cite the Booth algorithm and its variants, often used for low consumption circuits, and techniques generating all partial products before reducing them in a number of logarithmic stages according to the size of the inputs (such as the Wallace trees (in) et de dadda (in) ).

Principle [ modifier | Modifier and code ]

The algorithms used by current multipliers are improved variants of the column multiplication algorithm learned in small classes. The only difference lies in the multiplication table used. In binary, this multiplication table comes down to it:

• 
  ${displaystyle 0times 0=0}$

  

• 
  ${displaystyle 0times 1=0}$

  

• 
  ${displaystyle 1times 0=0}$

  

• 
  ${displaystyle 1times 1=1}$

  

For the rest, the algorithm is identical to that learned in primary. This consists in calculating partial products, each being equal to the product of one of the figures of the multiplier by the multiplicand. These partial products are then added all together to give the result.

Multipliers not signed [ modifier | Modifier and code ]

Multiplieur simple [ modifier | Modifier and code ]

The simplest multipliers implement the algorithm seen above the most trivial way there is, calculating the partial products and adding them one by one. These multipliers are therefore composed of an additional, and an accumulator to memorize temporary results. These incorporate registers to store the multiplicand and multiplier throughout the duration of the operation. The whole is seconded from a counter, responsible for managing the number of rehearsals that remains to be carried out before the end of the multiplication, and a little of the combinatorial logic to manage the start of the operation and its ending .

At the very beginning of the operation, the multiplier and the multiplicand are stored in registers, and the accumulator storing the result is initialized to zero. Then, with each clock cycle, the multiplier will calculate the partial product from the low weight bit of the multiplier, and the multiplicand. This calculation of the partial product is a simple and between each bit of the multiplicand, and the low weight bit of the multiplier. This partial product is then added to the content of the accumulator. At each cycle, the multiplier is shifted from a notch to the right, in order to switch to the following bit (as a reminder, the multiplication of the multiplicand is made by a bit of the multiplier at the same time). The multiplicand is also offset from a notch to the left.

The multiplier seen above can undergo some small optimizations. A first optimization consists in not performing a product between multiplicand and low weight bit of the multiplier if the latter is zero. In this case, the partial product will be zero, and its addition with the content of the unnecessary accumulator. We can perfectly be content to shift the contents of the multiplicand, without calculating the partial product and performing the addition. This can be done quite simply by using the combinatorial logic connected to the circuit, provided that it takes care of sequenced the discrepancies and order the additional. Similarly, if the low weight bit of the multiplier is not zero, it is useless to make the product (via and), the product is identical to the multiplicand.

It is therefore enough, at each clock cycle, if the low weight bit of the multiplier is not zero, to add the multiplicand to the content of the accumulator. At each cycle, the multiplier is shifted from a notch to the right, and the multiplicand is shifted from a notch to the left.

Shared multiplier [ modifier | Modifier and code ]

Another possible optimization is to store the result at the output of the additional not in the low weight bits of that, but in its strong weight bits. If we shift our accumulator from a notch to the right with each addition of partial product, we can obtain the right result. With this technique, you can use a smaller additional. For example, without this optimization, the multiplication of two numbers of 32 bit would require an additional capable of treating numbers of 64 bits. With optimization, a vulgar 32 -bit additional may be enough.

In this optimized multiplier, it is possible to merge the multiplier register and the accumulator. The trick of this circuit consists in storing the multiplier in the low weight bits of the merged register, and in placing the result at the output of the added in the bits of strong weight. At each cycle, the accumulator register is shifted to the right. The bits used by the multiplier are therefore gradually replaced by the result of the addition of the partial product. This merger allows you to use a simpler additional.

Multipliers tables [ modifier | Modifier and code ]

Instead of adding partial products one by one, it is also possible to perform them in parallel. Just use as many additions and calculation circuits for partial products as there are partial products to be calculated. We can thus calculate all partial products in parallel, and make the additions with a set of added added additions. Generally, these are reservoir -spread adders that are used in this type of circuits. The use of more advanced adders would far increase the amount of logic doors used by the final circuit, for a fairly low performance gain.

Nevertheless, chain serial adders thus uses many circuits. What is more, these adders have a significant propagation time. Gains in terms of performance exist compared to multipliers seen above, but do not necessarily deserve such an increase in the size of the circuit. To avoid wasting the place, it is possible to use so-called Carry-Save adders, designed to speed up multiple additions.

Multipliers with reduction trees [ modifier | Modifier and code ]

Reduction of partial products from an 8 -bit multiplication by a Wallace tree

To gain performance, and make the circuit faster, it is possible to make the addition of partial products not in series, but via a reduction tree. This tree takes advantage of the fact that three bits of the same weight in partial products can be added in two bits, one of which is of higher weight, and is just interested in the individual bits of partial products without trying to add two to two . We thus save the propagation of restraint, which is a cause of latency and complexity in adders. When it is no longer possible to reduce, we add the two groups of remaining figures.

For two numbers N -sized, as the number of figures for partial products is n² in total and the reduction takes a number of logarithmic stages, the reduction trees make it possible to make multiplication in one time

, as is the case for the addition. However, multipliers are in practice slower and imposing than adders.

There are various types of trees to reduce, the best known being Wallace trees as well as Dadda trees.

Signed multiplication [ modifier | Modifier and code ]