[{"@context":"http:\/\/schema.org\/","@type":"BlogPosting","@id":"https:\/\/wiki.edu.vn\/all2en\/wiki32\/operon-wikipedia\/#BlogPosting","mainEntityOfPage":"https:\/\/wiki.edu.vn\/all2en\/wiki32\/operon-wikipedia\/","headline":"OPERON – wikipedia","name":"OPERON – wikipedia","description":"before-content-x4 Otteron It is an X86 microprocessor for server and workstation produced by AMD. It was the first processor of","datePublished":"2018-12-28","dateModified":"2018-12-28","author":{"@type":"Person","@id":"https:\/\/wiki.edu.vn\/all2en\/wiki32\/author\/lordneo\/#Person","name":"lordneo","url":"https:\/\/wiki.edu.vn\/all2en\/wiki32\/author\/lordneo\/","image":{"@type":"ImageObject","@id":"https:\/\/secure.gravatar.com\/avatar\/44a4cee54c4c053e967fe3e7d054edd4?s=96&d=mm&r=g","url":"https:\/\/secure.gravatar.com\/avatar\/44a4cee54c4c053e967fe3e7d054edd4?s=96&d=mm&r=g","height":96,"width":96}},"publisher":{"@type":"Organization","name":"Enzyklop\u00e4die","logo":{"@type":"ImageObject","@id":"https:\/\/wiki.edu.vn\/wiki4\/wp-content\/uploads\/2023\/08\/download.jpg","url":"https:\/\/wiki.edu.vn\/wiki4\/wp-content\/uploads\/2023\/08\/download.jpg","width":600,"height":60}},"image":{"@type":"ImageObject","@id":"https:\/\/upload.wikimedia.org\/wikipedia\/commons\/thumb\/3\/34\/Quad-Core_AMD_Opteron_processor.jpg\/220px-Quad-Core_AMD_Opteron_processor.jpg","url":"https:\/\/upload.wikimedia.org\/wikipedia\/commons\/thumb\/3\/34\/Quad-Core_AMD_Opteron_processor.jpg\/220px-Quad-Core_AMD_Opteron_processor.jpg","height":"229","width":"220"},"url":"https:\/\/wiki.edu.vn\/all2en\/wiki32\/operon-wikipedia\/","wordCount":4757,"articleBody":"     (adsbygoogle = window.adsbygoogle || []).push({});before-content-x4Otteron It is an X86 microprocessor for server and workstation produced by AMD. It was the first processor of the K8 series and the first to implement a 64 -bit instructions set thanks to the AMD64 entertainment. The first version of Opteron (code name SledgeHammer ) was published on April 22, 2003 and intended to compete on the server and workstation market, in particular against the Intel Xeon and Itanium processors. A new generation of processors based on K10 micro -architecture (code name Barcelona ) and in a 4 -core configuration was announced on September 10, 2007. In February 2011, the most recent Opteron CPUs (code name Magny-Courses ) adopt 8 and 12 core configurations on Socket G34.        (adsbygoogle = window.adsbygoogle || []).push({});after-content-x4Table of ContentsKey features [ change | Modifica Wikitesto ] Characteristics of the multiprocessor systems [ change | Modifica Wikitesto ] Opteron multi core [ change | Modifica Wikitesto ] Socket [ change | Modifica Wikitesto ] Update of the micro -architecture [ change | Modifica Wikitesto ] Otteron (130 Nm Soi) [ change | Modifica Wikitesto ] Otteron (90 Nm Soi, DDR) [ change | Modifica Wikitesto ] Otteron (90 Nm Soi, DDR2) [ change | Modifica Wikitesto ] Otteron (65 Nm Soi) [ change | Modifica Wikitesto ] Otteron (45 Nm Soi) [ change | Modifica Wikitesto ] Otteron privi di opm [ change | Modifica Wikitesto ] Recall of some models [ change | Modifica Wikitesto ] Key features [ change | Modifica Wikitesto ] One of the main features of this CPU is to be able to perform 32 -bit programs without speed decrements, at the same time offering compatibility with 64 -bit software and the possibility of accessing more than 4 GB of RAM memory (one of the limits 32 -bit X86 processors). At the time of its introduction, this combination of factors gave Opteron a significant performance advantage over ITANIUM processors and first generation 64 -bit xeon (code name Nocoma ) which were clearly slower in the execution of 32 -bit native software. In addition, although they have been available for years – on the server\/workstation market – 64 -bit microprocessors -based microprocessors (SPARC, Alpha, PA -RISC, POWERPC, MIPS) the adoption of the X86 instructions set guaranteed – at low costs – the Compatibility with the vast base of X86 software installed by allowing, in this way, to the AMD CPU to obtain a positive recognition on the market. Another feature of Opteron is the integrated memory controller. This component, usually included in the Northbridge, puts the CPU in communication with memory. The implementation in the processor’s die, in addition to reducing the costs of the chipsets, makes sure that the electrical signals no longer have to travel the front side bus to the Northbridge and, from there, towards the memory (and vice versa), but allows one Direct communication with the RAM by reducing its latency and improving the overall system performance.        (adsbygoogle = window.adsbygoogle || []).push({});after-content-x4Characteristics of the multiprocessor systems [ change | Modifica Wikitesto ] In multiprocessor systems (two or more processors on a single motherboard), the CPUs use the Direct Connect Architecture architecture to communicate with the input\/output subsystem through high speed links of the Hypertransport bus. In this way, each microprocessor can access the main memory of the other in a completely transparent way to the programmer. The OPTERON approach to the Multiprocessor Systems is of a non-uniform memory access (Numa) and differs from the most common symmetrical multiprocessor architecture; The RAM of the system, in fact, is not equally accessible to all processors, but each CPU has its own memory benches. The OPTERON CPU natively supports 8 -way multiprocessor systems (8 CPUs on a single card), but Enterprise band servers use routing systems that can extend support to a greater number of CPU per module. Several benchmarks highlight a better scalability of the Opteron multiprocessor systems compared to the Intel Xeon counterparts of the generations preceding the Bloomfield series. [first] Since each Opteron has its own controller and RAM benches, the addition of new CPUs increases, in fact, gradually the band’s width of memory; The OPTERON CPUs also use an internal switch to divide the processes rather than a shared common bus and the integration of the memory controller guarantees faster access to the RAM. On the contrary, the XEONs share only two buses for processor-processor communication and processor-member; Consequently, the growth of the number of CPUs, competition between microprocessors for access to common resources produces a decrease in global system efficiency. To remedy the problem, in November 2008, Intel was migrated to a memory architecture similar to that of the Opteron starting from the XEON processors (35xx and subsequent series) that are based on Neham’s micro -architecture. Opteron multi core [ change | Modifica Wikitesto ] The die of an Optteron four -core processor. The die of an Opteron six -core processor. On April 21, 2005, the Sunnyvale company presented the first multi core version (8Yy series Egypt on Socket 940) of its server class processor. This generation of Opteron consisted of 90 Nm dual core processors which integrated two separated L1 and L2 cache and a common memory controller; Despite the presence of two cores, heat dissipation remained on the same levels (TDP of 85-95 W) of the fastest single core series (2yy series Troy , Serie 8yy Athens ) which used the same production process. The adoption of a dual core architecture (and subsequently multicore) doubled the performance for single socket, consequently decreasing the cost of setting up a multiprocessor system; The cost of the motherboard for this type of systems, in fact, grows considerably with the increase in the number of socket.        (adsbygoogle = window.adsbygoogle || []).push({});after-content-x4At the time of its introduction, the fastest multi -core model was the Otteron 875 (2.2 GHz dual core); The faster single core model of the same period was, however, the Otteron 252 At 2.6 GHz. Despite the lower speed of the 875 model, the Dual Core architecture guaranteed it higher performance compared to 252 both in the multithtaded applications and in the execution of many single thread applications. The second generation of Optteron Dual Core at 90 Nm (12yy series Santa Ana , serie 22yy e 82yy Santa Rosa ) implemented support for DDR2 memories and adopted two new socket models: the Am2 socket for the 12xx series that supported single processor configurations and the socket F for models Santa Rosa which supported both double processor configurations (22yy series) and four or eight processors (82yy series). AMD launched the third generation of Opteron Multi Core (Quad Core at 65 Nm) in September 2007. Based on core design with a code name Barcelona , the new series supported Double processor Quad Core configurations on Socket F with a nearby TDP (95-119 W) to previous dual core solutions. A further productive step (45 Nm) was reached in April\/June 2009 with the release of new four and six core models belonging, respectively, to the 23YY and 83YY series Shanghai and to the 24yy series Istanbul . In February 2011, the most performing OPTERON series is 61yy Magny-Courses 45 Nm on Socket G34. These 8 and 12 core CPUs on a multi-chip module consist of two die to 4 and 6 cores interconnected with each other through a Hypertransport link (version 3.1); They support DDR3 memories and a greater speed of the Hypertransport link that reaches 3.20 GHz (6.40 GT\/s) against 2.40 GHz (4.80 gt\/s) of the series Istanbul . Socket [ change | Modifica Wikitesto ] The first version of Opteron adopted the Socket 940 which remained the reference connector for all single core models. In August 2005, two series were also released (1yy Venus single core and 1yy Denmark Dual Core) on Socket 939 – the same connector of the Athlon 64 CPUs of the time – intended for the low -cost server and workstation market. Except for the 1 MB L2 cache (against 512 KB of Athlon 64), these CPUs were identical to the Athlon with core design San Diego It is Toledo , but had a clock speed lower than that supported by the cores in order to increase operating stability. The Am2 Socket was introduced in the Opteron line in 2006 through the 12Yy series Santa Ana . These 90 Nm dual core processors supported only single processor configurations and had a double -sized L2 cache (2×1 MB) compared to that of the Athlon 64 x2 fees in the home sector. Also in 2006, the Opteron on Socket F were introduced which remained the reference connector for all the multi core series from 2 up to 6 cores (code names Santa Rosa , Barcelona , Shanghai It is Istanbul ) and with construction processes at 90, 65 and 45 Nm which were released between 2006 and 2009. The new connector presented a Land Grid Array interface with 1207 contacts (mechanically identical, but generally not compatible with the 1207 FX variant of the same Socket) which, unlike the most classic PGA, provided that the interconnection pins were welded directly to the connector (and therefore on the motherboard) instead of the processor. The new socket introduced, in the Opteron line, the support to the DDR2 memory and the 3.X version of the Hypertransport bus. In April 2008, AMD introduced three Opteron Quad Core models on Socket Am2+ (Code name Budapest ) for single processor server. It was 65 Nm CPU with speeds between 2.1 and 2.3 GHz and similar to the series Alena of the Phenom Quad Core. The B2 stepping model was suffering from the same bug at the Translation Lookaside Buffer that afflicted all the B2 revisions of the Phenom family.In June 2009, AMD presented three Optteron Quad Core models at 45 Nm on Socket Am3 (Code name Suzuka ) always intended for the single processor server market. These processors, similar to the series Deneb of the Phenom II family, they had clock speeds between 2.5 and 2.9 Ghz. Between 2010 and 2011, AMD introduces two new series of 45 Nm multicore processors on Socket C32 (LGA with 1207 contacts) and Socket G34 (LGA with 1944 contacts). Socket C32 (41yy series Lisbon at 4 and 6 cores in a double processor configuration) supports the DDR3 memory; Although physically similar to Socket F, it is mapped in such a way as to prevent the accidental listing of CPUs for Socket F (which support only DDR2 memory). The Socket G34 (61yy series Magny-Courses 8 and 12 cores in a 2 and 4 processors configuration) supports four DDR3 memory channels (two channels for Die) and it is also expected to use the future versions of Opteron such as the series Interlagos of the family Bulldozer . Unlike previous sockets, the traditional support for RAM etc. is also added to the one to the not recorded memories ( unbuffered ) and non-Ecc. Update of the micro -architecture [ change | Modifica Wikitesto ] The Opteron line has witnessed, starting from 2007 with the series Barcelona , also to the implementation of AMD K10 micro -architecture. The new processors incorporate a series of improvements compared to the previous K8 architecture in particular in the prefetch of memory, and in the speculative execution skills, simd and prediction of the branches that increase its performance in the parallel calculation while maintaining the same profile of the previous generation in terms of consumption. [2] With the K10 architecture, AMD has also introduced a new scheme for the evaluation of the average electrical consumption of the processors called Averal Cpu Power (ACP). All Opteron for Socket 940 and 939 are branded with a model number ( model number ) three -digit expressed in the form Otteron Xyy . The OPTERON for subsequent socket adopts, however, a four -digit model number in the form Otteron Xzyy . For the first, second and third generation OPTERON, the first figure ( X ) indicates the number of CPUs supported by the reference system: first – Designed for single processor systems 2 – Designed for two processors systems 8 – Designed for 4 or 8 processors systems For Opteron on Socket F, Am2, Am2+ and Am3 the second figure ( WITH ) represents the generation of the processor: 2 – dual core, DDR2 3 – quad core, DDR2 4 – six cores, ddr2 The Opteron on Socket C32 and G34 adopt, however, a new four -digit scheme. The first figure ( X ) always indicates the number of CPUs supported by the reference system, but with a different nomenclature: 4 – Designed for single and double processor systems 6 – Designed for two and four processing systems The second figure ( WITH ) indicates the generation of the processor: first It refers to the models based on K10 architecture ( Magny-Courses and Lisbon ) while the number 2 It is reserved for models based on architecture Bulldozer . For all models, the figures YY They indicate the relative clock frequency between the processors of a given series for which higher values \u200b\u200bcorrespond to higher operating frequencies. The numerical indication is comparable exclusively between CPU of the same generation and with the same number of cores. The suffix HE O Of indicates, respectively, the models ad high efficiency ed energy efficiency ( high-efficiency It is energy-efficiency ) with a lower TDP profile than the standard OPTERON. The suffix With Instead, it indicates the top of the range models with a TDP higher than the Opteron Standard. With the transition to the 65 Nm production system, the code name of the Opteron resumes the name of the cities that host the Grand Prix of Formula 1 (AMD for a long time sponsors the Ferrari team). Family of AMD OPTERON processors Series (code name) Construction process Introduction Type SledgeHammer Venus Troy Athens 130\u00a0nm 90\u00a0nm 90\u00a0nm 90\u00a0nm Judo 2003 Ago 2005 Gen 2006 Gen 2006 Single core Denmark Italy Egypt Santa Ana Santa Rosa 90\u00a0nm 90\u00a0nm 90\u00a0nm 90\u00a0nm 90\u00a0nm Mar 2006 Mag 2006 Judo 2006 Ago 2006 Ago 2006 Dual core Barcelona Budapest Shanghai 65\u00a0nm 65\u00a0nm 45\u00a0nm Set 2007 Apr 2008 Nov 2008 Quad core Istanbul 45\u00a0nm JURAN 2009 Esa core Magny-Courses 45\u00a0nm Mar 2010 Octa core Magny-Courses 45\u00a0nm Mar 2010 Dodeca Core Otteron (130 Nm Soi) [ change | Modifica Wikitesto ] Single core \u2013 SledgeHammer (1yy, 2yy, 8yy) Stepping: B3, C0, CG L1 cache: 64 + 64 KB (data + instructions) L2 cache: 1024 KB at full speed MMX, 3DNOW! Extended, SSE, SSE2, AMD64 Socket 940, 800 MHz Hypertransport DDR SDRAM Recorded request, etc. supported VCORE: 1.50 V – 1.55 V Maximum consumption (TDP): 89 W Clock frequency: 1,4\u20132.4 GHz (x40 – x50) Introduction: April 22, 2003 [first] Otteron (90 Nm Soi, DDR) [ change | Modifica Wikitesto ] Single core \u2013 Venus (1yy), Troy (2yy), Athens (8YY) Stepping: E4 L1 cache: 64 + 64 KB (data + instructions) L2 cache: 1024 KB at full speed MMX, 3DNOW! Extended, SSE, SSE2, SSE3, AMD64 Socket 940, 800 MHz Hypertransport Socket 939\/Socket 940, 1000 MHz Hypertransport DDR SDRAM Registered Request for Socket 940, Supported etc. VCORE: 1.35 V – 1.4 V Maximum consumption (TDP): 95 W NX Bit Controls of the 64 -bit segment limit for VMware X86 virtualization. Optimized Power Management (OPM) Clock frequency: 1.6 – 3.0 GHz (x42 – x56) Introduction: February 14, 2005 Dual core \u2013 Denmark (1yy), Italy (2yy), Egypt (8YY) Stepping: E1, E6 Clock frequency: 1,6\u20132.8 GHz (X60, X65, X70, X75, X80, X85, X90) .. Socket 939\/Socket 940, 1000 MHz Hypertransport .. NX bit Introduction: spring 2005 Otteron (90 Nm Soi, DDR2) [ change | Modifica Wikitesto ] Dual core \u2013 Santa Ana (12yy), Santa Rosa (22yy, 82yy) Steping: F2, F3 L1 cache: 64 + 64 KB (data + instructions) L2 cache: 2*1024 KB at full speed MMX, 3DNOW! Extended, SSE, SSE2, SSE3, AMD64 Socket F, 1000 MHz HyperTransport – Opteron 2yy, 8yy Socket AM2, 1000 MHz HyperTransport – Opteron 1yy VCORE: 1.35 V Maximum consumption (TDP): 95 W NX Bit AMD-V virtualization Optimized Power Management (OPM) Frequenza di clock: 1,8\u20133,2\u00a0GHz (xx10, xx12, xx14, xx16, xx18, xx20, xx22, xx24) Introduction: 2006 Otteron (65 Nm Soi) [ change | Modifica Wikitesto ] Quad core \u2013 Barcelona (23xx, 83xx) 2360\/8360 and subsequent, Budapest (13yy) 1356 and subsequent Stepping: BA, B3 L1 cache: 64 + 64 KB (data + instructions) for cores L2 cache: 512 KB, at full speed per core L3 cache: 2048 KB, shared MMX, 3DNOW! Extended, SSE, SSE2, SSE3, AMD64, SSE4A Socket F, Socket AM2+, HyperTransport 3.0 (1,6\u00a0GHz-2\u00a0GHz) DDR2 SDRAM Registered Request, Supported etc. VCORE: 1.2 V Maximum consumption (TDP): 119 W NX Bit Second generation AMD-V virtualization with Rapid Virtualization Indexing (RVI) Dual Dynamic Power Management (DDPM): separate power supply for cores and memory controller Introduction: September 10, 2007 Clock frequency: 1.7\u20132.5 GHz Otteron (45 Nm Soi) [ change | Modifica Wikitesto ] Quad core \u2013 Shanghai (23xx, 83xx) 2370\/8370 and subsequent, Suzuka (13yy) 1381 and subsequent Stepping: C2 Cache L3: 6 MB, Condivisa Clock frequency: 2,3\u20132.9 Ghz Hypertropport 1.0, 3.0 20% reduction in energy consumption in idle mode [2] DDR2-800 memory support (Socket F) [3] DDR3-1333 memory support (socket am3) Esa core – Istanbul (24xx, 84xx) Introduction: June 1, 2009 Stepping: D0 Cache L3: 6 MB, Condivisa Clock frequency: 2,2\u20132.8 GHz Hyperopport 3.0 HT\u2013Assist DDR2-800 memory support [4] Octa core \u2013 Magny-Courses Mcm (6124-6136) Introduction: March 29, 2010 Stepping: D1 L3 cache: 2×6 MB, shared Clock frequency: 2.0\u20132.4 GHz Quattro link HyperTransport 3.1 a 3,2\u00a0GHz (6,40 GT\/s) HT\u2013Assist DDR3-1333 memory support Socket G34 Dodeca Core – Magny-Courses Mcm (6164-6176) Introduction: March 29, 2010 Stepping: D1 L3 cache: 2×6 MB, shared Clock frequency: 1,7\u20132.3 Ghz Quattro link HyperTransport 3.1 a 3,2\u00a0GHz (6,40 GT\/s) HT\u2013Assist DDR3-1333 memory support Socket G34 Quad core \u2013 Lisbon (4122, 4130) Introduction: June 23, 2010 Stepping: D0 Cache L3: 6 MB Clock frequency: 2.2 GHz (4122), 2.6 GHz (4130) Due link HyperTransport a 3,2\u00a0GHz (6,40 GT\/s) HT-Assist DDR3-1333 memory support Socket C32 Esa core – Lisbon (4162-4184) Introduction: June 23, 2010 Stepping: D1 Cache L3: 6 MB Clock frequency: 1,7-2.8 Ghz Due link HyperTransport a 3,2\u00a0GHz (6,40 GT\/s) HT-Assist DDR3-1333 memory support Socket C32 The following Supercomputer based on Opteron are mentioned among the 10 fastest supercomputer in the world in the top 500 ranking of November 2010 (the bold number indicates the position in the standings): [3] 2 : Jaguar – Cray XT5 (Opteron 6-core a 2,6\u00a0GHz; 10,4 GFlops\/unit\u00e0; 224\u00a0162 core totali; Rmax: \t1759,00 TFlops; Rpeak: 2331,00 TFlops). Cray Installato presso l’Oak Ridge National Laboratory, USA. 5 : Hopper – Cray XE6 (Opteron 12-core a 2,1\u00a0GHz; 8,4 GFlops\/unit\u00e0; 153\u00a0408 core totali; Rmax: \t1054,00 TFlops; Rpeak: 1288,63 TFlops). Cray Inc. Installato presso il Lawrence Berkeley National Laboratory \/ National Energy Research Scientific Computing Center, USA. 7 : IBM Roadrunner (Opteron Dual Core at 1.8 GHz; IBM Powerxcell 8i at 3.2 GHz; 12.8 GFLOPS\/Unit per cell; 122 400 total cores; RMAX: 1042.00 TFLOPS; Rpeak: 1375.78 TFLOPS). IBM. Installed at the Los Alamos National Laboratory, USA. The IBM Roadrunner uses 6 912 Opteron Dual Core processors. 432 OPTERON are used for system management operations, while the other 6 480 processors are interconnected with each other and the related cores are connected to 12 960 IBM Powerxcell 8i processors. The roadrunner is considered a Cluster Opteron computer with Cell accelerator, where each node consists of a cell processor connected to an OPTERON core. 8 : Kraken – Cray XT5 (Opteron 6-core at 2.6 GHz; 10.4 GFLOPS\/Unit; 98 928 Total cores; RMAX: 831.70 TFLOPS; Rpeak: 1028.85 TFLOPS). Cray Inc. installed at the National Institute for Computational Sciences, University of Tennessee, USA. ten : Sky – cray xe6 (Opteron 8-core at 2.4 GHz; 9.6 GFLOPS\/Unit; 107 152 Total cores; RMAX: 816.60 TFLOPS; Rpeak: 1028.66 TFLOPS). Cray Inc. installed at the Los Alamos National Laboratory, USA. Otteron privi di opm [ change | Modifica Wikitesto ] AMD has released some OPTERON (indicated in the table) that do not support technology Optimized Power Management (OPM). The processors equipped with OPM reduce energy consumption and heat production automatically regulating the core voltage and clock frequency. Maximum frequency of p-states Minimum frequency of p-states Model Socket Core # TDP (W) Construction process Standard number (OPN) 1400\u00a0MHz \u00a0N\/A 140 Socket 940 first 82.1 130 nm OSA140CEP5AT 1400\u00a0MHz \u00a0N\/A 240 Socket 940 first 82.1 130\u00a0nm Osa240Cep5au 1400\u00a0MHz \u00a0N\/A 840 Socket 940 first 82.1 130\u00a0nm OSA840CEP5AV 1600\u00a0MHz \u00a0N\/A 142 Socket 940 first 82.1 130\u00a0nm OSA142CEP5AT 1600\u00a0MHz \u00a0N\/A 242 Socket 940 first 82.1 130\u00a0nm Osa242cep5au 1600\u00a0MHz \u00a0N\/A 842 Socket 940 first 82.1 130\u00a0nm OSA842CEP5AV 1600\u00a0MHz \u00a0N\/A 242 Socket 940 first 85.3 90 nm Osa242faa5bl 1600\u00a0MHz \u00a0N\/A 842 Socket 940 first 85.3 90\u00a0nm Osa842faa5BM 1600\u00a0MHz \u00a0N\/A 260 Socket 940 2 55.0 90\u00a0nm OSK260FAA6CB 1600\u00a0MHz N\/A 860 Socket 940 2 55.0 90\u00a0nm OSKSOPERMENT Recall of some models [ change | Modifica Wikitesto ] AMD has recalled some OPTERON Single Core processors with Stepping E4, including X52 (2.6 GHz) and X54 (2.8 GHz) models which use DDR memory. The following table indicates the attracted processors, as indicated in the production notes of AMD Opteron X52 and X54. [4] Maximum frequency of p-states Single processor Double processor Multi processor Socket 2600\u00a0MHz 152 252 852 Socket 940 2800\u00a0MHz \u00a0N\/A 254 854 Socket 940 2600\u00a0MHz 152 \u00a0N\/A \u00a0N\/A Socket 939 2800\u00a0MHz 154 \u00a0N\/A \u00a0N\/A Socket 939 The indicated processors can produce inconsistent results when the following conditions are simultaneously needed:       (adsbygoogle = window.adsbygoogle || []).push({});after-content-x4"},{"@context":"http:\/\/schema.org\/","@type":"BreadcrumbList","itemListElement":[{"@type":"ListItem","position":1,"item":{"@id":"https:\/\/wiki.edu.vn\/all2en\/wiki32\/#breadcrumbitem","name":"Enzyklop\u00e4die"}},{"@type":"ListItem","position":2,"item":{"@id":"https:\/\/wiki.edu.vn\/all2en\/wiki32\/operon-wikipedia\/#breadcrumbitem","name":"OPERON – wikipedia"}}]}]