[{"@context":"http:\/\/schema.org\/","@type":"BlogPosting","@id":"https:\/\/wiki.edu.vn\/en\/wiki21\/cast-32a-wikipedia\/#BlogPosting","mainEntityOfPage":"https:\/\/wiki.edu.vn\/en\/wiki21\/cast-32a-wikipedia\/","headline":"CAST-32A – Wikipedia","name":"CAST-32A – Wikipedia","description":"before-content-x4 From Wikipedia, the free encyclopedia Multi-core Processors Abbreviation CAST-32A Year started 2014 Latest version ANovember\u00a02016\u00a0(2016-11) Organization FAA Domain Aviation","datePublished":"2017-01-01","dateModified":"2017-01-01","author":{"@type":"Person","@id":"https:\/\/wiki.edu.vn\/en\/wiki21\/author\/lordneo\/#Person","name":"lordneo","url":"https:\/\/wiki.edu.vn\/en\/wiki21\/author\/lordneo\/","image":{"@type":"ImageObject","@id":"https:\/\/secure.gravatar.com\/avatar\/c9645c498c9701c88b89b8537773dd7c?s=96&d=mm&r=g","url":"https:\/\/secure.gravatar.com\/avatar\/c9645c498c9701c88b89b8537773dd7c?s=96&d=mm&r=g","height":96,"width":96}},"publisher":{"@type":"Organization","name":"Enzyklop\u00e4die","logo":{"@type":"ImageObject","@id":"https:\/\/wiki.edu.vn\/wiki4\/wp-content\/uploads\/2023\/08\/download.jpg","url":"https:\/\/wiki.edu.vn\/wiki4\/wp-content\/uploads\/2023\/08\/download.jpg","width":600,"height":60}},"image":{"@type":"ImageObject","@id":"https:\/\/en.wikipedia.org\/wiki\/Special:CentralAutoLogin\/start?type=1x1","url":"https:\/\/en.wikipedia.org\/wiki\/Special:CentralAutoLogin\/start?type=1x1","height":"1","width":"1"},"url":"https:\/\/wiki.edu.vn\/en\/wiki21\/cast-32a-wikipedia\/","wordCount":2872,"articleBody":"     (adsbygoogle = window.adsbygoogle || []).push({});before-content-x4From Wikipedia, the free encyclopediaMulti-core ProcessorsAbbreviationCAST-32AYear started2014Latest versionANovember\u00a02016\u00a0(2016-11)OrganizationFAADomainAviationWebsitefaa.gov       (adsbygoogle = window.adsbygoogle || []).push({});after-content-x4CAST-32A, Multi-core Processors is a position paper,[1] by the Certification Authorities Software Team (CAST). It is not official guidance, but is considered informational by certification authorities such as the FAA and EASA. A key point is that Multi-core processor “interference can affect execution timing behavior, including worst case execution time (WCET).”[2]The original document was published in 2014 by an “international group of certification and regulatory authority representatives.”[3]  The current revision A was released in 2016. “The Federal Aviation Administration (FAA) and European Aviation Safety Agency (EASA) worked with industry to quantify a set of requirements and guidance that should be met to certify and use multi-core processors in civil aviation, described e.g. in the FAA CAST-32A Position Paper and the EASA Use of MULticore proCessORs in airborne Systems (MULCORS) research report.”[4]For applicants certifying under EASA, AMC 20-193 has now superseded CAST-32A since its release on 21 January 2022. It is expected that the FAA will release its Advisory Circular AC 20-193 guidance in 2023, which is expected to be almost identical to AMC 20-193.[5][6]       (adsbygoogle = window.adsbygoogle || []).push({});after-content-x4One of the first mixed-criticality multicore avionics systems is expected to be certified sometime in 2020.[7] The objectives of the standard are applicable to software on multicore processors, including the operating system.[8][9] However, the nature of the underlying processor hardware must be examined in detail to identify potential interference channels due to inter-core contention for shared resources.[10] Verification that multicore interference channels have been mitigated can be accomplished through the use of interference generators i.e. software tuned to create a heavy usage pattern on a shared resource.[11] By creating stress on the shared resource, the impact of contention between cores can be measured and quantified.[12]Objectives[edit]The paper presents ten objectives that must be met for Design Assurance Level (DAL) A or B. Six of the objectives apply for DAL C.  The paper does not apply for DAL D or E. [1]ObjectiveApplicable Design Assurance LevelsMCP Planning 1A, B, CMCP Resource Usage 1A, B, CMCP Resource Usage 2A, BMCP Planning 2A, B, CMCP Resource Usage 3A, BMCP Resource Usage 4A, BMCP Software 1A, B, CMCP Software 2A, B, CMCP Error Handling 1A, BMCP Accomplishment Summary 1A, B, CReferences[edit]^ a b “Multi-core Processors” (PDF). CAST-32A. Federal Aviation Administration. 1 November 2016. Retrieved 23 March 2020.^ VanderLeest, Steven H.; Evripidou, Christos (10 March 2020). “An Approach to Verification of Interference Concerns for Multicore Systems (CAST-32A)”. SAE Technical Paper Series. Vol.\u00a01. SAE International. pp.\u00a01174\u20131181. doi:10.4271\/2020-01-0016. S2CID\u00a0213352079. Retrieved 11 March 2020.^ K\u00fchlert, Oliver (11 February 2020). “Multi-Core Ready to Become Airborne”. Embedded Computing Design.^ Athavale, Jyotika; Mariani, Riccardo; Paulitsch, Michael (19 March 2019). “Flight Safety Certification Implications for Complex Multi-Core Processor Based Avionics Systems”. 2019 IEEE International Reliability Physics Symposium (IRPS). IEEE: 1\u20136. doi:10.1109\/IRPS.2019.8720422. ISBN\u00a0978-1-5386-9504-3. S2CID\u00a0169037813.^ Wolfe, Frank (28 February 2020). “EASA and FAA to Issue Further Guidance on Multicore Certification This Year”. Avionics International. Retrieved 9 March 2020.^ “Certification Authorities Software Team (CAST)”. Federal Aviation Administration. Retrieved 29 October 2021.^ Radack, David; Tiedeman, Jr., Harold G.; Parkinson, Paul (2018). “Civil Certification of Multi-core Processing Systems in Commercial Avionics”. Rockwell Collins. Retrieved 23 March 2020.^ “DDC-I and Rapita Systems Simplify Verification and Certification of Multicore Avionics Applications”. 21 April 2020. Retrieved 23 March 2020.^ Brown, Mark (15 November 2018). “CAST=32A: Significance and Implications”. Retrieved 11 December 2020.^ Agirre, Irune; Abella, Jaume; Azkarate-askasua, Mikel; Cazorla, Francisco (14 June 2017). “On the Tailoring of CAST-32A CertificationGuidance to Real COTS Multicore Architectures”. IEEE. Retrieved 23 March 2020.^ VanderLeest, Steven H.; Evripidou, Christos (10 March 2020). “An Approach to Verification of Interference Concerns for Multicore Systems”. SAE International Journal of Advances and Current Practices in Mobility. SAE. 2 (3): 1174\u20131181. doi:10.4271\/2020-01-0016. S2CID\u00a0213352079. Retrieved 23 March 2020.^ Wright, Daniel (10 November 2019). “Multicore Timing Analysis for DO-178C”. Rapita systems. Retrieved 17 January 2022.       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