[{"@context":"http:\/\/schema.org\/","@type":"BlogPosting","@id":"https:\/\/wiki.edu.vn\/en\/wiki24\/list-of-arm-processors-wikipedia\/#BlogPosting","mainEntityOfPage":"https:\/\/wiki.edu.vn\/en\/wiki24\/list-of-arm-processors-wikipedia\/","headline":"List of ARM processors – Wikipedia","name":"List of ARM processors – Wikipedia","description":"Product family ARM architecture Processor Feature Cache (I\u00a0\/\u00a0D), MMU Typical MIPS @ MHz Reference ARM1 ARMv1 ARM1 First implementation None","datePublished":"2019-06-24","dateModified":"2019-06-24","author":{"@type":"Person","@id":"https:\/\/wiki.edu.vn\/en\/wiki24\/author\/lordneo\/#Person","name":"lordneo","url":"https:\/\/wiki.edu.vn\/en\/wiki24\/author\/lordneo\/","image":{"@type":"ImageObject","@id":"https:\/\/secure.gravatar.com\/avatar\/c9645c498c9701c88b89b8537773dd7c?s=96&d=mm&r=g","url":"https:\/\/secure.gravatar.com\/avatar\/c9645c498c9701c88b89b8537773dd7c?s=96&d=mm&r=g","height":96,"width":96}},"publisher":{"@type":"Organization","name":"Enzyklop\u00e4die","logo":{"@type":"ImageObject","@id":"https:\/\/wiki.edu.vn\/wiki4\/wp-content\/uploads\/2023\/08\/download.jpg","url":"https:\/\/wiki.edu.vn\/wiki4\/wp-content\/uploads\/2023\/08\/download.jpg","width":600,"height":60}},"image":{"@type":"ImageObject","@id":"https:\/\/wiki.edu.vn\/wiki4\/wp-content\/uploads\/2023\/08\/download.jpg","url":"https:\/\/wiki.edu.vn\/wiki4\/wp-content\/uploads\/2023\/08\/download.jpg","width":100,"height":100},"url":"https:\/\/wiki.edu.vn\/en\/wiki24\/list-of-arm-processors-wikipedia\/","wordCount":3833,"articleBody":"Product familyARM architectureProcessorFeatureCache (I\u00a0\/\u00a0D), MMUTypical MIPS @ MHzReferenceARM1ARMv1ARM1First implementationNoneARM2ARMv2ARM2ARMv2 added the MUL (multiply) instructionNone0.33 DMIPS\/MHzARM2aSARMv2aARM250Integrated MEMC (MMU), graphics and I\/O processor. ARMv2a added the SWP and SWPB (swap) instructionsNone, MEMC1aARM3First integrated memory cache4\u00a0KB unified0.50 DMIPS\/MHzARM6ARMv3ARM60ARMv3 first to support 32-bit memory address space (previously 26-bit).ARMv3M first added long multiply instructions (32×32=64).None10\u00a0MIPS @ 12\u00a0MHzARM600As ARM60, cache and coprocessor bus (for FPA10 floating-point unit)4\u00a0KB unified28\u00a0MIPS @ 33\u00a0MHzARM610As ARM60, cache, no coprocessor bus4\u00a0KB unified17\u00a0MIPS @ 20\u00a0MHz0.65 DMIPS\/MHz[4]ARM7ARMv3ARM700coprocessor bus (for FPA11 floating-point unit)8\u00a0KB unified40\u00a0MHzARM710As ARM700, no coprocessor bus8\u00a0KB unified40\u00a0MHz[5]ARM710aAs ARM710, also used as core of ARM71008\u00a0KB unified40\u00a0MHz0.68 DMIPS\/MHzARM7TARMv4TARM7TDMI(-S)3-stage pipeline, Thumb, ARMv4 first to drop legacy ARM 26-bit addressingNone15\u00a0MIPS @ 16.8\u00a0MHz63 DMIPS @ 70\u00a0MHzARM710TAs ARM7TDMI, cache8\u00a0KB unified, MMU36\u00a0MIPS @ 40\u00a0MHzARM720TAs ARM7TDMI, cache8\u00a0KB unified, MMU with FCSE (Fast\u00a0Context Switch Extension)60\u00a0MIPS @ 59.8\u00a0MHzARM740TAs ARM7TDMI, cacheMPUARM7EJARMv5TEJARM7EJ-S5-stage pipeline, Thumb, Jazelle DBX, enhanced DSP instructionsNoneARM8ARMv4ARM8105-stage pipeline, static branch prediction, double-bandwidth memory8\u00a0KB unified, MMU84\u00a0MIPS @ 72\u00a0MHz1.16 DMIPS\/MHz[6][7]ARM9TARMv4TARM9TDMI5-stage pipeline, ThumbNoneARM920TAs ARM9TDMI, cache16\u00a0KB \/ 16\u00a0KB, MMU with FCSE (Fast Context Switch Extension)200\u00a0MIPS @ 180\u00a0MHz[8]ARM922TAs ARM9TDMI, caches8\u00a0KB \/ 8\u00a0KB, MMUARM940TAs ARM9TDMI, caches4\u00a0KB \/ 4\u00a0KB, MPUARM9EARMv5TEARM946E-SThumb, enhanced DSP instructions, cachesVariable, tightly coupled memories, MPUARM966E-SThumb, enhanced DSP instructionsNo cache, TCMsARM968E-SAs ARM966E-SNo cache, TCMsARMv5TEJARM926EJ-SThumb, Jazelle DBX, enhanced DSP instructionsVariable, TCMs, MMU220\u00a0MIPS @ 200\u00a0MHzARMv5TEARM996HSClockless processor, as ARM966E-SNo caches, TCMs, MPUARM10EARMv5TEARM1020E6-stage pipeline, Thumb, enhanced DSP instructions, (VFP)32\u00a0KB \/ 32\u00a0KB, MMUARM1022EAs ARM1020E16\u00a0KB \/ 16\u00a0KB, MMUARMv5TEJARM1026EJ-SThumb, Jazelle DBX, enhanced DSP instructions, (VFP)Variable, MMU or MPUARM11ARMv6ARM1136J(F)-S8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), enhanced DSP instructions, unaligned memory accessVariable, MMU740 @ 532\u2013665\u00a0MHz (i.MX31 SoC), 400\u2013528\u00a0MHz[9]ARMv6T2ARM1156T2(F)-S9-stage pipeline, SIMD, Thumb-2, (VFP), enhanced DSP instructionsVariable, MPU[10]ARMv6ZARM1176JZ(F)-SAs ARM1136EJ(F)-SVariable, MMU + TrustZone965 DMIPS @ 772\u00a0MHz, up to 2,600\u00a0DMIPS with four processors[11]ARMv6KARM11MPCoreAs ARM1136EJ(F)-S, 1\u20134 core SMPVariable, MMUSecurCoreARMv6-MSC000As Cortex-M00.9 DMIPS\/MHzARMv4TSC100As ARM7TDMIARMv7-MSC300As Cortex-M31.25 DMIPS\/MHzCortex-MARMv6-MCortex-M0Microcontroller profile, most Thumb + some Thumb-2,[12] hardware multiply instruction (optional small), optional system timer, optional bit-banding memoryOptional cache, no TCM, no MPU0.84 DMIPS\/MHz[13]Cortex-M0+Microcontroller profile, most Thumb + some Thumb-2,[12] hardware multiply instruction (optional small), optional system timer, optional bit-banding memoryOptional cache, no TCM, optional MPU with 8 regions0.93 DMIPS\/MHz[14]Cortex-M1Microcontroller profile, most Thumb + some Thumb-2,[12] hardware multiply instruction (optional small), OS option adds SVC \/ banked stack pointer, optional system timer, no bit-banding memoryOptional cache, 0\u20131024\u00a0KB I-TCM, 0\u20131024\u00a0KB D-TCM, no MPU136 DMIPS @ 170\u00a0MHz,[15] (0.8\u00a0DMIPS\/MHz FPGA-dependent)[16][17]ARMv7-MCortex-M3Microcontroller profile, Thumb \/ Thumb-2, hardware multiply and divide instructions, optional bit-banding memoryOptional cache, no TCM, optional MPU with 8 regions1.25 DMIPS\/MHz[18]ARMv7E-MCortex-M4Microcontroller profile, Thumb \/ Thumb-2 \/ DSP \/ optional VFPv4-SP single-precision FPU, hardware multiply and divide instructions, optional bit-banding memoryOptional cache, no TCM, optional MPU with 8 regions1.25 DMIPS\/MHz (1.27 w\/FPU)[19]Cortex-M7Microcontroller profile, Thumb \/ Thumb-2 \/ DSP \/ optional VFPv5 single and double precision FPU, hardware multiply and divide instructions0\u221264\u00a0KB I-cache, 0\u221264\u00a0KB D-cache, 0\u201316\u00a0MB I-TCM, 0\u201316\u00a0MB D-TCM (all these w\/optional ECC), optional MPU with 8 or 16 regions2.14 DMIPS\/MHz[20]ARMv8-M BaselineCortex-M23Microcontroller profile, Thumb-1 (most), Thumb-2 (some), Divide, TrustZoneOptional cache, no TCM, optional MPU with 16 regions1.03 DMIPS\/MHz[21]ARMv8-M MainlineCortex-M33Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processorOptional cache, no TCM, optional MPU with 16 regions1.50 DMIPS\/MHz[22]Cortex-M35PMicrocontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processorBuilt-in cache (with option 2\u201316\u00a0KB), I-cache, no TCM, optional MPU with 16 regions1.50 DMIPS\/MHz[23]ARMv8.1-M MainlineCortex-M551.69 DMIPS\/MHz[24]ARMv8.1-M MainlineCortex-M853.13 DMIPS\/MHz[25]Cortex-RARMv7-RCortex-R4Real-time profile, Thumb \/ Thumb-2 \/ DSP \/ optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses \/ cache \/ TCM, 8-stage pipeline dual-core running lockstep with fault logic0\u201364\u00a0KB \/ 0\u201364\u00a0KB, 0\u20132 of 0\u20138\u00a0MB TCM, opt. MPU with 8\/12 regions1.67 DMIPS\/MHz[26][27]Cortex-R5Real-time profile, Thumb \/ Thumb-2 \/ DSP \/ optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses \/ cache \/ TCM, 8-stage pipeline dual-core running lock-step with fault logic \/ optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP)[28]0\u201364\u00a0KB \/ 0\u201364\u00a0KB, 0\u20132 of 0\u20138\u00a0MB TCM, opt. MPU with 12\/16 regions1.67 DMIPS\/MHz[26][29]Cortex-R7Real-time profile, Thumb \/ Thumb-2 \/ DSP \/ optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses \/ cache \/ TCM, 11-stage pipeline dual-core running lock-step with fault logic \/  out-of-order execution \/ dynamic register renaming \/ optional as 2 independent cores, low-latency peripheral port (LLPP), ACP[28]0\u201364\u00a0KB \/ 0\u201364\u00a0KB,\u00a0? of 0\u2013128\u00a0KB TCM, opt. MPU with 16 regions2.50 DMIPS\/MHz[26][30]Cortex-R8TBD0\u201364 KB \/ 0\u201364 KB L1, 0\u20131 \/ 0\u20131 MB TCM, opt MPU with 24 regions2.50 DMIPS\/MHz[26][31]ARMv8-RCortex-R52TBD0\u201332 KB \/ 0\u201332 KB L1, 0\u20131 \/ 0\u20131 MB TCM, opt MPU with 24+24 regions2.16 DMIPS\/MHz[32][33]Cortex-R82TBD16\u2013128 KB \/16\u201364 KB L1, 64K\u20131MB L2, 0.16\u20131 \/ 0.16\u20131 MB TCM,opt MPU with 32+32 regions3.41 DMIPS\/MHz[34][35]Cortex-A(32-bit)ARMv7-ACortex-A5Application profile, ARM \/ Thumb \/ Thumb-2 \/ DSP \/ SIMD \/ Optional VFPv4-D16 FPU \/ Optional NEON \/ Jazelle RCT and DBX, 1\u20134 cores \/ optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)4\u221264\u00a0KB \/ 4\u221264\u00a0KB L1, MMU + TrustZone1.57\u00a0DMIPS\/MHz per core[36]Cortex-A7Application profile, ARM \/ Thumb \/ Thumb-2 \/ DSP \/ VFPv4 FPU \/ NEON \/ Jazelle RCT and DBX \/ Hardware virtualization, in-order execution, superscalar, 1\u20134 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), architecture and feature set are identical to A15, 8\u201310 stage pipeline, low-power design[37]8\u221264\u00a0KB \/ 8\u221264\u00a0KB L1, 0\u20131\u00a0MB L2, MMU + TrustZone1.9 DMIPS\/MHz per core[38]Cortex-A8Application profile, ARM \/ Thumb \/ Thumb-2 \/ VFPv3 FPU \/ NEON \/ Jazelle RCT and DAC, 13-stage superscalar pipeline16\u201332\u00a0KB \/ 16\u201332\u00a0KB L1, 0\u20131\u00a0MB L2 opt. ECC, MMU + TrustZoneUp to 2000 (2.0\u00a0DMIPS\/MHz in speed from 600\u00a0MHz to greater than 1\u00a0GHz)[39]Cortex-A9Application profile, ARM \/ Thumb \/ Thumb-2 \/ DSP \/ Optional VFPv3 FPU \/ Optional NEON \/ Jazelle RCT and DBX, out-of-order speculative issue superscalar, 1\u20134 SMP cores, MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)16\u201364\u00a0KB \/ 16\u201364\u00a0KB L1, 0\u20138\u00a0MB L2 opt. parity, MMU + TrustZone2.5 DMIPS\/MHz per core, 10,000\u00a0DMIPS @ 2\u00a0GHz on Performance Optimized TSMC 40G (dual-core)[40]Cortex-A12Application profile, ARM \/ Thumb-2 \/ DSP \/ VFPv4 FPU \/ NEON \/ Hardware virtualization, out-of-order speculative issue superscalar, 1\u20134 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)32\u221264 KB3.0 DMIPS\/MHz per core[41]Cortex-A15Application profile, ARM \/ Thumb \/ Thumb-2 \/ DSP \/ VFPv4 FPU \/ NEON \/ integer divide \/ fused MAC \/ Jazelle RCT \/ hardware virtualization, out-of-order speculative issue superscalar, 1\u20134 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline[37]32\u00a0KB w\/parity \/ 32\u00a0KB w\/ECC L1, 0\u20134\u00a0MB L2, L2 has ECC, MMU + TrustZoneAt least 3.5\u00a0DMIPS\/MHz per core (up to 4.01\u00a0DMIPS\/MHz depending on implementation)[42][43]Cortex-A17Application profile, ARM \/ Thumb \/ Thumb-2 \/ DSP \/ VFPv4 FPU \/ NEON \/ integer divide \/ fused MAC \/ Jazelle RCT \/ hardware virtualization, out-of-order speculative issue superscalar, 1\u20134 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP32 KB L1, 256\u00a0KB\u20138\u00a0MB L2 w\/optional ECC2.8\u00a0DMIPS\/MHz[44]ARMv8-ACortex-A32Application profile, AArch32, 1\u20134 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline8\u201364\u00a0KB w\/optional parity \/ 8\u221264\u00a0KB w\/optional ECC L1 per core, 128\u00a0KB\u20131\u00a0MB L2 w\/optional ECC shared[45]Cortex-A(64-bit)ARMv8-ACortex-A34Application profile, AArch64, 1\u20134 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline8\u221264\u00a0KB w\/parity \/ 8\u221264\u00a0KB w\/ECC L1 per core, 128\u00a0KB\u20131\u00a0MB L2\u00a0shared, 40-bit physical addresses[46]Cortex-A35Application profile, AArch32 and AArch64, 1\u20134 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline8\u221264\u00a0KB w\/parity \/ 8\u221264\u00a0KB w\/ECC L1 per core, 128\u00a0KB\u20131\u00a0MB L2\u00a0shared, 40-bit physical addresses1.78 DMIPS\/MHz[47]Cortex-A53Application profile, AArch32 and AArch64, 1\u20134 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline8\u221264\u00a0KB w\/parity \/ 8\u221264\u00a0KB w\/ECC L1 per core, 128\u00a0KB\u20132\u00a0MB L2\u00a0shared, 40-bit physical addresses2.3 DMIPS\/MHz[48]Cortex-A57Application profile, AArch32 and AArch64, 1\u20134 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width decode superscalar, deeply out-of-order pipeline48 KB w\/DED parity \/ 32\u00a0KB w\/ECC L1 per core; 512\u00a0KB\u20132\u00a0MB L2\u00a0shared w\/ECC; 44-bit physical addresses4.1\u20134.8\u00a0DMIPS\/MHz[49][50][51]Cortex-A72Application profile, AArch32 and AArch64, 1\u20134 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width superscalar, deeply out-of-order pipeline48 KB w\/DED parity \/ 32\u00a0KB w\/ECC L1 per core; 512\u00a0KB\u20132\u00a0MB L2\u00a0shared w\/ECC; 44-bit physical addresses6.3-7.3 DMIPS\/MHz[52][53]Cortex-A73Application profile, AArch32 and AArch64, 1\u20134 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width superscalar, deeply out-of-order pipeline64 KB \/ 32\u221264\u00a0KB L1 per core, 256\u00a0KB\u20138\u00a0MB L2\u00a0shared w\/ optional ECC, 44-bit physical addresses7.4-8.5 DMIPS\/MHz[52][54]ARMv8.2-ACortex-A55Application profile, AArch32 and AArch64, 1\u20138 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline[55]16\u221264 KB \/ 16\u221264\u00a0KB L1, 256\u00a0KB L2 per core, 4\u00a0MB L3 shared3 DMIPS\/MHz[52][56]Cortex-A65Application profile, AArch64, 1\u20138 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-wide decode superscalar, 3-width issue, out-of-order pipeline, SMT[57]Cortex-A65AEAs ARM Cortex-A65, adds dual core lockstep for safety applications64 \/ 64 KB L1, 256\u00a0KB L2 per core, 4\u00a0MB L3 shared[58]Cortex-A75Application profile, AArch32 and AArch64, 1\u20138 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width decode superscalar, deeply out-of-order pipeline[59]64 \/ 64 KB L1, 512\u00a0KB L2 per core, 4\u00a0MB L3 shared8.2-9.5 DMIPS\/MHz[52][60]Cortex-A76Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1\u20134 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 8-way issue, 13 stage pipeline, deeply out-of-order pipeline[61]64 \/ 64 KB L1, 256\u2212512\u00a0KB L2 per core, 512\u00a0KB\u22124\u00a0MB L3 shared10.7-12.4 DMIPS\/MHz[52][62]Cortex-A76AEAs ARM Cortex-A76, adds dual core lockstep for safety applications[63]Cortex-A77Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1\u20134 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 6-width instruction fetch, 12-way issue, 13 stage pipeline, deeply out-of-order pipeline[61]1.5K L0 MOPs cache, 64 \/ 64\u00a0KB L1, 256\u2212512\u00a0KB L2 per core, 512\u00a0KB\u22124\u00a0MB L3 shared13-16 DMIPS\/MHz[64][65]Cortex-A78[66]Cortex-A78AEAs ARM Cortex-A78, adds dual core lockstep for safety applications[67]Cortex-A78C[68]ARMv9-ACortex-A510Cortex-A710[69]Cortex-A715Cortex-XARMv8.2-ACortex-X1Performance-tuned variant of Cortex-A78ARMv9-ACortex-X2Cortex-X3NeoverseARMv8.2-ANeoverse N1Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1\u20134 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 8-way dispatch\/issue, 13 stage pipeline, deeply out-of-order pipeline[61]64 \/ 64 KB L1, 512\u22121024\u00a0KB L2 per core, 2\u2212128\u00a0MB L3 shared, 128\u00a0MB system level cache[70]Neoverse E1Application profile, AArch64, 1\u20138 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-wide decode superscalar, 3-width issue, 10 stage pipeline, out-of-order pipeline, SMT32\u221264 KB \/ 32\u221264\u00a0KB L1, 256\u00a0KB L2 per core, 4\u00a0MB L3 shared[71]ARMv8.4-ANeoverse V1[72]ARMv9-ANeoverse N2[73]ARM familyARM architectureARM coreFeatureCache (I\u00a0\/\u00a0D), MMUTypical MIPS @ MHzReference"},{"@context":"http:\/\/schema.org\/","@type":"BreadcrumbList","itemListElement":[{"@type":"ListItem","position":1,"item":{"@id":"https:\/\/wiki.edu.vn\/en\/wiki24\/#breadcrumbitem","name":"Enzyklop\u00e4die"}},{"@type":"ListItem","position":2,"item":{"@id":"https:\/\/wiki.edu.vn\/en\/wiki24\/list-of-arm-processors-wikipedia\/#breadcrumbitem","name":"List of ARM processors – Wikipedia"}}]}]