Unum (number format) – Wikipedia

Project

author

Type Precisions Quire

Support?

Speed Testing Notes GP-GPU

VividSparks

World’s First FPGA GP-GPU 32 Yes ~3.2 Tpops Exhaustive. No known bugs. RacEr GP-GPU has 512 cores SoftPosit

A*STAR

C library based on Berkeley SoftFloat

C++ wrapper to override operators
Python wrapper using SWIG of SoftPosit

8, 16, 32 published and complete; Yes ~60 to 110 Mpops/s on x86 core (Broadwell) 8: Exhaustive;

16: Exhaustive except FMA, quire
32: Exhaustive test is still in progress.
No known bugs.

Open source license. Fastest and most comprehensive C library for posits presently. Designed for plug-in comparison of IEEE floats and posits. posit4.nb

A*STAR

Mathematica notebook All Yes < 80 kpops/s Exhaustive for low precisions. No known bugs. Open source (MIT license). Original definition and prototype. Most complete environment for comparing IEEE floats and posits. Many examples of use, including linear solvers posit-javascript

A*STAR

JavaScript widget Convert decimal to posit 6, 8, 16, 32; generate tables 2–17 with es 1–4. — —; interactive widget Fully tested Table generator and conversion Universal

Stillwater Supercomputing, Inc

C++ template library

C library
Python wrapper
Golang library

Arbitrary precision posit float valid (p)

Unum type 1 (p)
Unum type 2 (p)

Arbitrary quire configurations with programmable capacity posit<4,0> 1 GPOPS

posit<8,0> 130 MPOPS
posit<16,1> 115 MPOPS
posit<32,2> 105 MPOPS
posit<64,3>
50 MPOPS
posit<128,4>
1 MPOPS
posit<256,5>
800 kPOPS

Complete validation suite for arbitrary posits

Randoms for large posit configs.
Uses induction to prove nbits+1 is correct
no known bugs

Open source. MIT license.

Fully integrated with C/C++ types and automatic conversions.
Supports full C++ math library (native and conversion to/from IEEE).
Runtime integrations: MTL4/MTL5, Eigen, Trilinos, HPR-BLAS.
Application integrations: G+SMO, FDBB, FEniCS, ODEintV2, TVM.ai.
Hardware Accelerator integration (Xilinx, Intel, Achronix).

Speedgo

Chung Shin Yee

Python library All No ~20 Mpops/s Extensive; no known bugs Open source (MIT license) softposit-rkt

David Thien

SoftPosit bindings for Racket All Yes Un­known Un­known sfpy

Bill Zorn

SoftPosit bindings for Python All Yes ~20–45 Mpops/s on 4.9 GHz Skylake core Un­known positsoctave

Diego Coelho

Octave Implementation All No Un­known Limited Testing; no known bugs GNU GPL Sigmoid Numbers

Isaac Yonemoto

Julia library All <32, all ES Yes Un­known No known bugs (posits).

Division bugs (valids)

Leverages Julia’s templated mathematics standard library, can natively do matrix and tensor operations, complex numbers, FFT, DiffEQ. Support for valids FastSigmoid

Isaac Yonemoto

Julia and C/C++ library 8, 16, 32, all ES No Un­known Known bug in 32-bit multiplication Used by LLNL in shock studies SoftPosit.jl

Milan Klöwer

Julia library Based on softposit;

8-bit (es=0..2)
16-bit (es=0..2)
24-bit (es=1..2)
32-bit
(es=2)

Yes Similar to

A*STAR
“SoftPosit”
(Cerlane Leong)

Yes:

Posit (8,0),
Posit (16,1),
Posit (32,2)
Other formats lack full functionality

Open source. Issues and suggestions on GitHub.

This project was developed due to the fact that SigmoidNumbers and FastSigmoid by Isaac Yonemoto is not maintained currently.

Supports basic linear algebra functions in Julia (Matrix multiplication, Matrix solve, Elgen decomposition, etc.)

PySigmoid

Ken Mercado

Python library All Yes < 20 Mpops/s Un­known Open source (MIT license). Easy-to-use interface. Neural net example. Comprehensive functions support. cppPosit

Emanuele Ruffaldi

C++ library 4 to 64 (any es value); “Template version is 2 to 63 bits” No Un­known A few basic tests 4 levels of operations working with posits. Special support for NaN types (nonstandard) bfp:Beyond Floating Point

Clément Guérin

C++ library Any No Un­known Bugs found; status of fixes unknown Supports + – × ÷ √ reciprocal, negate, compare Verilog.jl

Isaac Yonemoto

Julia and Verilog 8, 16, 32, ES=0 No Un­known Comprehensively tested for 8-bit, no known bugs Intended for Deep Learning applications Addition, Subtraction and Multiplication only. A proof of concept matrix multiplier has been built, but is off-spec in its precision Lombiq Arithmetics

Lombiq Technologies

C# with Hastlayer for hardware generation 8, 16, 32.

(64bits in progress)

Yes 10 Mpops/s

Click here for more

Partial Requires Microsoft .Net APIs DeepfloatJeff Johnson, Facebook SystemVerilog Any (parameterized SystemVerilog) Yes —

(RTL for FPGA/ASIC designs)

Limited Does not strictly conform to posit spec.

Supports +,-,/,*. Implements both logarithmic posit and normal, “linear” posits
License: CC-BY-NC 4.0 at present

Tokyo Tech FPGA 16, 32, extendable No “2 GHz”, not translated to Mpops/s Partial; known rounding bugs Yet to be open-source PACoGen: Posit Arthmetic Core GeneratorManish Kumar Jaiswal Verilog HDL for Posit Arithmetic Any precision.

Able to generate any combination of word-size (N) and exponent-size (ES)

No Speed of design is based on the underlying hardware platform (ASIC/FPGA) Exhaustive tests for 8-bit posit.

Multi-million random tests are performed for up to 32-bit posit with various ES combinations

It supports rounding-to-nearest rounding method. Vinay Saxena, Research and Technology Centre, Robert Bosch, India (RTC-IN) and Farhad Merchant, RWTH Aachen University Verilog generator for VLSI, FPGA All No Similar to floats of same bit size N=8

– ES=2 | N=7,8,9,10,11,12
Selective (20000*65536) combinations for
– ES=1 | N=16

To be used in commercial products. To the best of our knowledge.

***First ever integration of posits in RISC-V***

Posit Enabled RISC-V Core

(Sugandha Tiwari, Neel Gala, Chester Rebeiro, V.Kamakoti, IIT MADRAS)

BSV (Bluespec System Verilog) Implementation 32-bit posit with (es=2) and (es=3) No — Verified against SoftPosit for (es=2) and tested with several applications for (es=2) and (es=3). No known bugs. First complete posit capable RISC-V core. Supports dynamic switching between (es=2) and (es=3).

More info here.

PERCIVAL

David Mallasén

Open-Source Posit RISC-V Core with Quire Capability Posit<32,2> with 512-bit quire Yes Speed of design is based on the underlying hardware platform (ASIC/FPGA) Functionality testing of each posit instruction. Application-level posit capable RISC-V core based on CVA6 that can execute all posit instructions, including the quire fused operations. PERCIVAL is the first work that integrates the complete posit ISA and quire in hardware. It allows the native execution of posit instructions as well as the standard floating-point ones simultaneously. LibPosit

Chris Lomont

Single file C# MIT Licensed Any size No Extensive; no known bugs Ops: arithmetic, comparisons, sqrt, sin, cos, tan, acos, asin, atan, pow, exp, log unumjl

REX Computing

FPGA version of the “Neo” VLIW processor with posit numeric unit 32 No ~1.2 Gpops/s Extensive; no known bugs No divide or square root. First full processor design to replace floats with posits. PNU: Posit Numeric Unit

Calligo Tech

• Octacore RISC-V with Posit as PNU implemented on FPGA, demonstrated in HiPC 2022.
• ASIC implementation of Octacore RISC-V + PNU expected mid 2023.

• <32, 2> with Quire 512 bits support.
• <64, 3>

Yes – Fully supported. Benchmark in progress. Exhaustive tests completed for 32 bits and 64 bits with Quire support completed. Fully integrated with C/C++ types and automatic conversions. Supports full C++ math library (native and conversion to/from IEEE). Runtime integrations: GNU Utils, OpenBLAS, CBLAS. Application integrations: in progress. Compiler Support extended: C/C++, G++, GFortran & LLVM (in progress). IBM-TACC

Jianyu Chen

Specific-purpose FPGA 32 Yes 16–64 Gpops/s Only one known case tested Does 128-by-128 matrix-matrix multiplication (SGEMM) using quire. Deep PeNSieve

Raul Murillo

Python library (software) 8, 16, 32 Yes Un­known Un­known A DNN framework using posits Gosit

Jaap Aarts

Pure Go library 16/1 32/2 (included is a generic 32/ES for ES<32)^{[clarification needed]} No 80 Mop/s for div32/2 and similar linear functions. Much higher for truncate and much lower for exp. Fuzzing against c softposit with a lot of iterations for 16/1 and 32/2. Explicitly testing edge cases found. (MIT license) The implementations where ES is constant the code is generated. The generator should be able to generate for all sizes {8,16,32} and ES below the size. However, the ones not included into the library by default are not tested, fuzzed, or supported. Feel free use the generator to generate them for you, report bugs, supply patches, etc. For some operations on 32/ES, mixing and matching ES is possible. However, this is not tested.